Smart Grid Node with Remote Fault Detection

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NeuroStimCore Board
Figure 1: PCB 3D

Overview

The Smart Grid Node is a custom-designed embedded system for real-time voltage and current monitoring, fault detection, and remote telemetry in decentralized electrical infrastructure. Built around the STM32F103C8T6 microcontroller, the node features precision analog sensing, GPS-synchronized real-time clock logging, isolated CAN communication, and power regulation for distributed deployments. It enables scalable fault diagnosis and telemetry across smart grid environments with robust sensor interfaces and data logging capabilities.

Key Features

Voltage & Current Sensing

NeuroStimCore Board
Figure 2: Power Regulation and Voltage Sensing Schematic
NeuroStimCore Board
Figure 3: Current Sensing Schematic

The system monitors critical AC/DC grid lines using precision resistor dividers and current sense amplifiers. Voltage levels are scaled down via high-impedance dividers and filtered with RC stages before reaching the ADC. For current measurement, a shunt resistor feeds into an INA219 current sensor, selected for its I2C interface, built-in ADC, and 0.1% precision current measurement capability.

RTC-GPS Synchronization

NeuroStimCore Board
Figure 4: RTC + GPS Sync Schematic

A DS3231 real-time clock logs time-stamped events onto a microSD card. To ensure sub-second global accuracy, a GPS module's 1PPS signal is fed into the RTC or MCU to periodically resynchronize timestamps, a key requirement for grid-wide fault correlation and timing diagnostics.

ESP32 BLE Communication Interface

NeuroStimCore Board
Figure 5: ESP32 BLE Logging

To modernize telemetry and remote diagnostics, the Smart Grid Node integrates the ESP32-WROOM-32E module as its primary wireless interface. This module provides robust Bluetooth Low Energy (BLE) communication, chosen for its:

BLE was preferred over traditional CAN due to:

The ESP32 was connected directly to the STM32 via UART and optionally via SPI for high-throughput streaming. A UART bridge protocol was implemented using DMA on the STM32 side to reduce CPU overhead and allow bidirectional messaging with minimal latency.

Isolation and Safety

To protect the ESP32 from transients and ESD events common in power electronics environments:

Antenna & Layout

Special care was taken in PCB layout (see Figure 8):

Advantages

Power Regulation

As seen in Figure 1, the board accepts unregulated 12VDC input and regulates to 5V and 3.3V via AMS1117 LDOs. To prevent overcurrent faults, each rail is protected with resettable polyfuses. Strategic ferrite beads isolate analog and digital domains, minimizing coupling noise from high-frequency switching or telemetry bursts.

Data Logging System

A microSD slot stores sampled data with timestamps for offline analysis. Logging is triggered during predefined voltage/current anomalies or by manual command via CAN. The SD card operates over SPI and is interfaced using a dedicated chip-select to avoid contention during CAN activity.

PCB Layout Strategy

NeuroStimCore Board
Figure 6: PCB 2d

The 6-layer PCB follows a structure of Power + Signal, Power1, Power2 (VCC_3V3 pour), Signal1, Signal2 (unused), and GND. Analog sensing lines are shielded with ground pours and routed away from CAN and MCU switching traces. Clock and reset lines are short, terminated, and isolated from high-current planes. A star-grounding approach ensures low return-path impedance, and decoupling capacitors are placed within 2mm of each IC.

NeuroStimCore Board
Figure 7: GND Pour
NeuroStimCore Board
Figure 8: 3V3 Pour

Challenges & Future Work

Tools & Skills Used

Transformer-Based Fault Detection for Smart Grid Node

This project implements a self-supervised Transformer-based neural network for real-time fault detection on a custom Smart Grid Node PCB. The system performs embedded anomaly recognition from raw voltage and current waveforms, enabling low-latency fault detection without external supervision or cloud inference.

Both the paper and model repo can be found in the links above.

System Overview

Model Architecture

The model uses a Transformer encoder with 3 layers, 4 attention heads, and sinusoidal positional encodings. Trained exclusively on normal signals, the model learns to forecast future signal trajectories using next-step prediction. Faults are detected via elevated reconstruction error — measured as the deviation between predicted and observed voltages and currents.

Self-Supervised Training Pipeline

A custom dataset of synthetic 1-second waveforms (1 kHz sampling) was generated, containing normal and fault conditions such as overvoltage, undervoltage, disconnect, flicker, and drift. Only normal data was used during training. A frozen standard scaler was applied for normalization, and dynamic thresholding was used during inference.

Deployment

The model was quantized and converted to .tflite format. Inference was deployed on the STM32 microcontroller using TensorFlow Lite Micro, with rolling 1-second input windows. Faults were detected every 100 ms based on anomaly score thresholds and transmitted over BLE for immediate response.

Evaluation & Results

This approach enables interpretable, real-time fault detection directly on edge microcontrollers, without fault labels or cloud processing. Unlike threshold-based or supervised models, the self-supervised Transformer generalizes to unseen disruptions, offers visual insight into fault timing via attention heads, and operates entirely within the constraints of embedded hardware. This makes it a robust and scalable solution for intelligent grid diagnostics in future decentralized power networks.