HIL-Testing Rig

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The HIL (Hardware-in-the-Loop) Testing Rig is a custom-designed emulation board aimed at accelerating embedded system validation and debugging for safety-critical applications. The rig enables real-time injection of analog/digital faults, emulation of sensor input/output via DAC and ADC components, high-throughput logging via SPI Flash, and telemetry through USB and CAN interfaces. It is built around the STM32F103C8T6 microcontroller and designed with a modular 6-layer stackup to isolate analog, power, and digital zones. The system supports rapid iteration cycles for embedded firmware by simulating real-world scenarios through precisely controlled test signals.

NeuroStimCore Board
Figure 1: PCB 3D

Key Features

The HIL Testing Rig was designed from first principles to simulate sensor, actuator, and fault conditions that embedded systems experience in real-time deployments. The following subsystems were added with careful consideration for functional fidelity, hardware test coverage, and compatibility with industry debugging tools.

DAC + ADC Emulation I/O

NeuroStimCore Board
Figure 2: DAC + ADC Emulation Schematic

I included dual 12-bit DACs (MCP4922) and 16-bit ADCs (ADS1118) to simulate real-world analog input and output lines. The DACs drive test voltages into target MCU pins while the ADCs measure back-sensed voltages and responses. These components were selected for:

The DACs were buffered using dual-OPA280 op-amps to ensure consistent drive capability under varying load impedances. This guarantees accurate test voltage sourcing without droop or overshoot.

Fault Injection Subsystem

NeuroStimCore Board
Figure 3: Fault Injection Schematic

Fault injection logic was implemented using DIP switch arrays and analog switches (TS3A5018) to selectively short lines, introduce open conditions, or force stuck-at values. This design supports testing against edge-case scenarios such as:

These were wired in-line with the signal routing layer and mirrored with test headers for external instrumentation.

Power Management

NeuroStimCore Board
Figure 4: Power Management Schematic

The board accepts a 12V external input through a Molex Micro-Fit connector. A LDO (TLV7553) steps this down to 5V and 3.3V rails. Decoupling capacitors and ferrite beads isolate the analog and digital planes. This ensured:

Additional polyfuses protect each voltage domain against overcurrent events.

SPI Flash Logging

NeuroStimCore Board
Figure 5: SPI Flash Logging Schematic

An external 8MB SPI Flash (W25Q64JV) was included for logging waveform, event timing, or system responses during test runs. Chosen for its high throughput and endurance, this allows for offline inspection of:

Firmware logs data at configurable sampling rates and tags with event timestamps from a 32.768kHz-driven RTC.

STM32F103C8T6 Microcontroller

NeuroStimCore Board
Figure 6: STM32 Schematic

The core controller was chosen for its mature development ecosystem and peripheral availability:

Its Flash size and RAM were sufficient to buffer logs, interpret test scenarios, and drive peripherals in deterministic loops.

Test Headers

NeuroStimCore Board
Figure 7: Testing Headers

All internal signals—fault injection lines, DAC output, ADC input, and SPI interfaces—were routed to labeled 0.1" headers. This enabled quick:

Headers were isolated with series resistors and ESD diodes to avoid line interference.

USB + CAN Telemetry System

NeuroStimCore Board
Figure 8: Telemetry Schematic

To interface with host PCs or test control platforms, the board included:

USB was used for log retrieval and test initiation, while CAN enabled streaming status and triggering commands within larger HIL simulation clusters.

System Boot & Initialization

Fault Injection Logic

Control Pins

PCB Layout Strategy & Challenges

The HIL Testing Rig was laid out on a 6-layer PCB stackup to accommodate its dense analog-digital subsystems while maintaining signal integrity and power stability. The stackup was as follows:

NeuroStimCore Board
Figure 9: PCB 2D

Power was partitioned into separate islands for the analog front end (DAC/ADC/buffers), the MCU core logic, and the fault simulation logic. This minimized coupling between noisy switching traces and sensitive voltage sources. Decoupling was handled by placing high-frequency 0.1μF capacitors near every VDD pin and 10μF bulk capacitors per rail per zone.

CAN signals were routed on Layer 2 with matched impedance, using short stubs and differential trace pairs. Fault injection switches were centrally located, allowing short, symmetric routes to each simulated net. The DAC/ADC traces were routed over continuous ground and passed through low-pass filtering stages before test access.

Large copper pours were used to aid thermal dissipation, especially near the TPS54202 and polyfuse areas. SPI signal integrity was protected by series resistors and grounded shielding layers above and below Layer 4 traces.

NeuroStimCore Board
Figure 10: All Power + Signal Layers. Board outline polygon pour is 3.3 Volts Regulated.
NeuroStimCore Board
Figure 11: GND Layer

Design Challenges

Future Work